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PD17P401
PIN CONFIGURATION (Top View)
(1) Normal operating mode
LCD35 /P0D 1 /CKOUT
LCD23/COM 3
LCD24 /P1D0
LCD25 /P1D1
LCD26 /P1D2
LCD27 /P1D3
LCD28 /P1A 0
LCD29 /P1A 1
LCD30 /P1A 2
LCD31 /P1A 3
LCD32 /P0D0
LCD33 /P0D1
LCD34 /P0D2
COM 2
COM1
COM0
LCD20
LCD21
LCD22
LCD19 LCD18 LCD17 LCD16 LCD 15 /KS15 LCD 14 /KS14 LCD 13 /KS13 LCD 12 /KS12 LCD 11 /KS11 LCD 10 /KS10 LCD 9 /KS 9 LCD 8 /KS 8 LCD 7 /KS 7 LCD 6 /KS 6 LCD 5 /KS 5 LCD 4 /KS 4 LCD 3 /KS 3 LCD 2 /KS 2 LCD 1 /KS 1 LCD 0 /KS 0
1 2 3 4 5 6 7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
P0C 0
P0C 1 P0C 2 P0C 3 P2A 0 P2A 1/SI1 P2A 2/SCK 1 P2A 3/SO1 GND XT OUT XT IN V DD2 INT 1 INT 0 P0B 0 P0B 1 /ADC P0B 2 /RLS STOP P0B 0 /SI 0 P0A 0 /SO0 P0A 1 /SCK 0 P0A 2 /SCL
PD17P401GC-3B9
8 9 10 11 12 13 14 15 16 17 18 19
53 52 51 50 49 48 47 46 45 44 43 42
20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
IDC 2 /P1C 3
BLK 2 /P1C 2
IDC 1 /P1C 1
BLK 1 /P1C 0
2
P0A 3 /SDA
VSYNC
HSYNC
GND
OSC IN
OSC OUT
V DD1
X IN
X OUT
P1B3 /K 3
P1B2 /K 2
P1B1 /K 1
P1B0 /K 0
IDC 0
BLK 0
CE
PD17P401
(2) PROM programming mode
(Open)
1 2 3 4 5 6 7 8 9 (Open)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
MD0
D4
D5
D6
D7
D0
D1
D2
D3
MD1 MD2 MD3
(L)
GND (Open) (L) V DD2 (L) V PP
PD17P401GC-3B9
10 11 12 13 14 15 16 17 18 19
(L)
20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(Open)
GND
(L)
CLK
(Open)
(L)
(L)
V DD1
Note Items in parentheses indicate disposition of unused pins in the PROM programming mode. L : Connect to GND via an individual resistor (470 ). Leave open. Open:
(Open)
(L)
3
PD17P401
P0A0 to P0A3 P0B0 to P0B3 P0C0 to P0C3 P0D0 to P0D3 P1A0 to P1A3 P1B0 to P1B3 P1C0 to P1C3 P1D0 to P1D3 P2A0 to P2A3 KS0 to KS15 K0 to K3 : Input/output ports : Input/output ports : Input/output ports : Output ports : Output ports : Input/output ports : Output ports : Output ports : Input/output ports : Key source signal outputs : Key source signal return inputs VSYNC CLK MD0 to MD3 D0 to D7 VPP VDD1, VDD2 GND SCL SI0, SI1 SO0, SO1 SCK0, SCK1 XIN, XOUT XTIN, XTOUT IDC0 to IDC2 BLK0 to BLK2 HSYNC : Serial clock input/output : Serial data inputs : Serial data outputs : Serial clock input/outputs : Main clock oscillator : Sub-clock oscillator : IDC display signal outputs : Blanking signal outputs : Horizontal synchronization signal input : Vertical synchronization signal input : PROM clock input : PROM mode selection inputs : PROM data input/outputs : PROM power supply : Power supply : Ground
OSCIN, OSCOUT : IDC oscillator
LCD0 to LCD35 : LCD segment signal outputs COM0 to COM3: LCD common signal outputs CKOUT RLSSTOP CE INT0, INT1 ADC SDA : Sub-clock output : Stop mode release input : Chip enable input : External interrupt inputs : A/D converter input : Serial data input/output
4
PD17P401
BLOCK DIAGARAM
CPU Clock
XT IN XT OUT
OSC
32 kHz Clock Timer
8 bit Module Timer
X IN /CLK OSC X OUT
LCD 0 /KS 0 P0A 0 -P0A 3 RF P0B 0 -P0B 3 P0C0 /MD 0 P0C3 /MD 3 P0D0 -P0D 3 ALU SYSREG LCD Driver Port RAM 524 x 4 bits LCD 15 /KS 15 LCD16 LCD22 LCD 23 /COM 3 COM 2 COM 1 COM 0 LCD 24 /P1D 0 LCD 27 /P1D 3 P1B 0 -P1B 3 Instruction Decoder LCD 28 /P1A 0 /D4 LCD 31 /P1A 3 /D7 LCD 32 /P0D 0 /D0 LCD 35 /P0D 3 /CKOUT/D3 P1D 0 -P1D 3 One Time PROM 12288 x 16 bits
P1A 0 -P1A 3
P1C 0 -P1C 3
P2A 0 -P2A 3
IDC 2 /P1C 3 P0B 1 /ADC A /D Converter Program Counter BLK 2 /P1C 2 IDC 1 /P1C 1 Stack 7 x 13 bits BLK 1 /P1C 0 IDC IDC0 BLK 0 V SYNC RLS
STOP
INT 0 / V PP INT 1
Interrupt Control
H SYNC Reset Serial I/O 0 Serial I/O 1 OSC OUT OSC OSC IN
V DD1 V DD2 CE GND
P0A3 /SDA
P0A2 /SCL
P0A1 /SCK 0
P0A0 /SO 0
P0B 3 /SI 0
P2A3 /SO 1
P2A2 /SCK 1
P2A 1 /SI 1
5
PD17P401
CONTENTS
1. PIN FUNCTIONS ...........................................................................................................................
1.1 1.2 1.3 NORMAL OPERATING MODE ............................................................................................................ PROM PROGRAMMING MODE .......................................................................................................... PIN EQUIVALENT CIRCUITS ..............................................................................................................
7
7 10 11
2. LIST OF FUNCTIONS ................................................................................................................... 3. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ AND VERIFY OPERATIONS .......
3.1 3.2 3.3 PROGRAM MEMORY WRITE/READ/VERIFY OPERATING MODES .............................................. PROGRAM MEMORY WRITE PROCEDURE ...................................................................................... PROGRAM MEMORY READ PROCEDURE ........................................................................................
17 19
19 20 21
4. ELECTRICAL CHARACTERISTICS ............................................................................................... 5. PACKAGE DIMENSION ................................................................................................................ APPENDIX. DEVELOPMENT TOOLS ...............................................................................................
22 28 29
6
PD17P401
1. PIN FUNCTIONS
1.1 NORMAL OPERATING MODE
AFTER POWER-ON RESET
PIN NO.
SYMBOL
FUNCTION
OUTPUT TYPE
62 | 65 66 | 69 70 | 73 74 | 76 77 78 | 80 1 | 4 5 | 20
LCD controller/driver segment signal, LCD controller/driver common signal, key LCD35/P0D3/CKOUT matrix key source signal, port 0D, port 1A, | port 1D and watchdog timer 32 kHz crystal LCD32/P0D0 resonator oscillation signal outputs. LCD31/P1A3 * LCD35 to LCD0 | * LCD controller/driver segment signal LCD28/P1A0 outputs LCD27/P1D3 * COM0 to COM3 | * LCD controller/driver common signal LCD24/P1D0 outputs COM0 * KS15 to KS0 | * Key matrix key source signal outputs COM2 * P0D3 to P0D0 LCD23/COM3 * 4-bit CMOS output port LCD22 * P1A3 to P1A0 | * 4-bit CMOS output port LCD20 * P1D3 to P1D0 LCD19 * 4-bit CMOS output port | * CKOUT LCD16 * Watchdog timer 32 kHz oscillation LCD15/KS15 signal output | * Watchdog timer 32 kHz crystal LCD0/KS0 resonator (XTIN, XTOUT) oscillation frequency adjustment Port 1B and LCD segment key source signal return inputs. * P1B3 to P1B0 * 4-bit input/output port * Input/output set capability as a 4-bit unit * Internal pull-up resistor OFF * K3 to K0 * Key source signal return inputs * Internal pull-up resistor ON IDC (Image Display Controller) character display signal and blanking signal, and port 1C outputs. * IDC2 to IDC0 * Character display signal outputs * BLK2 to BLK0 * Character dispaly blanking signal outputs * P1C3 to P1C0
*
CMOS
Low-level output LCD35 to LCD0, COM0 to COM3
21 | 24
P1B3/K3 | P1B0/K0
Inputs with pull-up resistor
Input (P1B3 to P1B0)
25 26 27 28 29 30
IDC2/P1C3 BLK2/P1C2 IDC1/P1C1 BLK1/P1C0 IDC0 BLK0
CMOS push-pull
Low-level output IDC2 to IDC0, BLK2 to BLK0
4-bit CMOS output port
7
PD17P401
PIN NO. SYMBOL FUNCTION Inputs the IDC (Image Display Controller) vertical synchronization signal. Controls timing for output of the IDC character display signal and blanking signal. Should be made an active-low input. Either the rising edge or falling edge may be selected as the valid edge for an interrupt request. Inputs the IDC (Image Display Controller) horizontal synchronization signal. Controls timing for output of the IDC character display signal and blanking signal. Should be made an active-low input. Pins for ground. Pins 33 and 53 are connected within the chip, but should also be connected to the same potential externally taking into consideration the characteristics of the IDC (Image Display Controller). Connect the IDC (Image Display Controller) LC oscillator. This oscillation frequency is used to generate the character display signal. The oscillator is stopped when CE is low. Positive power supply. Applies 5 V 10 % in normal operation mode. Connect the system clock oscillator. A 10 MHz crystal resonator or ceramic resonator should be connected. OUTPUT TYPE AFTER POWER-ON RESET
31
VSYNC
--
Input
32
HSYNC
--
Input
33
GND
--
--
-- -- CMOS push-pull
34 35
OSCIN OSCOUT
36
VDD1
--
--
37 38
XIN XOUT
-- -- CMOS push-pull -- Input
39
CE
PD17P401 operation selection signal and reset signal input
8
PD17P401
PIN NO. SYMBOL FUNCTION Port 0A, port 0B, serial interface, clock stop release and A/D converter input/ outputs. * P0A3 to P0A0 * 4-bit input/output port * Input/output settable bit-wise * P0B3 to P0B0 * 4-bit CMOS input/output port * Input/output settable bit-wise * SDA, SCL * SDA : Serial data input/output * SCL : Serial clock input/output * SCK0, SO0, SI0 * SCK0 : Serial clock input/output * SO0 : Serial data output * SI0 : Serial data input * RLSSTOP * Clock stop release * ADC * Analog input to 6-bit resolution A/D converter Input external interrupt request signal. Either the rising edge or falling edge may be selected as the effective edge for an interrupt request. Watchdog 32 kHz oscillator power supply. Connects watchdog 32 kHz oscillator. A 32 kHz crystal resonator should be connected. Pin for ground. Pins 33 and 53 are connected within the chip, but should also be connected to the same potential externally taking into condideration the characteristics of the IDC (Image Display Controller). Port 2A and serial interface input/outputs. * P2A3 to P2A0 * 4-bit input/output port * Input/output set capability as bit-wise * SO1, SCK1, SI1 * SO1 : Serial data output * SCK1 : Serial clock input/output * SI1 : Serial data input 4-bit CMOS input/output port. Input/output set capability as bit-wise. OUTPUT TYPE AFTER POWER-ON RESET
N-ch open-drain VDD withstand voltage P0A3/SDA, P0A2/SCL
40 41 42 43 44 45 46 47
P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/RLSSTOP P0B1/ADC P0B0
CMOS push-pull P0A1/SCK0, P0A0/SO0, P0B3, P0B2/RLSSTOP, P0B1, P0B0
Input P0A3 to P0A0, P0B3 to P0B0
48 49
INT0 INT1
--
Input
50 51 52
VDD2 XTIN XTOUT
-- --
--
-- COMS push-pull
53
GND
--
--
54 55 57 58
P2A3/SO1 P2A2/SCK1 P2A1/SI1 P2A0
N-ch open-drain 16 V withstand voltage P2A3/SO1, P2A2/SCK1, P2A1, P2A0
Input (P2A3 to P2A0)
58 | 61
P0C3 | P0C0
CMOS push-pull
Input
9
PD17P401
1.2 PROM PROGRAMMING MODE
PIN NO.
SYMBOL
FUNCTION Ground. Pins 33 and 53 are connected within the chip, but should also be connected to the same potential externally. Positive power supply. Applies 6 V in grogram memory write, read and verify operations. PROM programming clock input. Positive power supply for PROM programming. Applies 12.5 V as program voltage in program memory write, read and verify operations. Positive power supply. Applies 6 V in program memory write, read and verify operations. Ground. Pins 33 and 53 are connected within the chip, but should also be connected to the same potential externally.
OUTPUT TYPE
33
GND
--
36 37 48
VDD1 CLK VPP
-- --
--
50
VDD2
--
53
GND
--
58 | 61 62 | 65 66 | 69
MD3 | MD0 D3 | D0 D7 | D4
Operating mode selection inputs for PROM programming.
--
PROM programming 8-bit data input/output.
CMOS push-pull
Remarks Pins other than the above are not used in the PROM programming mode. See "PIN CONFIGURATION (2) PROM PROGRAMMING MODE" for the disposition of unused pins.
10
PD17P401
1.3 1.3.1 PIN EQUIVALENT CIRCUITS P0A (P0A1/SCK0, P0A0/SO0) P0B (P0B3/SI0, P0B0) P0C (P0C3, P0C2, P0C1, P0C0)

(Input/output)
V DD
RES
V DD
1.3.2
P0B (P0B2/RLSSTOP) Input/output
V DD
RES
V DD
V DD
RLSSTOP
11
PD17P401
1.3.3 P0B (P0B1/ADC) (Input/output)
V DD
RES ADSEL V DD
A/D
1.3.4
P1B (P1B3, P1B2, P1B1, P1B0) (Input/output)
V DD High OnResistor
RES
V DD
12
PD17P401
1.3.5 P0A (P0A3/SDA, P0A2/SCL) (Input/output)
V DD
RES
1.3.6
P2A (P2A3/SO1, P2A2/SCK1, P2A1/SI1, P2A0) (Input/output)
V DD
RES
1.3.7
P1C (IDC2/P1C3, BLK2/P1C2, IDC1/P1C1, BLK1/P1C0) IDC0, BLK0
V DD
(Output)
13
PD17P401
1.3.8
(Input) INT1, INT0
CE
V DD
1.3.9
VSYNC, HSYNC (Input)
V DD
High OnResistor
RES
14
PD17P401
1.3.10 XIN (Input), XOUT (Output)
High OnResistor V DD V DD V DD RES
X IN
X OUT
1.3.11 OSCIN (Input), OSCOUT (Output)
V DD V DD V DD V DD ON/OFF1 ON/OFF2
OSC IN
V DD
OSC OUT
15
PD17P401
1.3.12 XTIN (Input), XTOUT (Output)
High OnResistor V DD V DD
XT IN
XT OUT POC
1.3.13 LCD23/COM3, COM2, COM1, COM0 (Output)
V DD V DD
1.3.14 LCD35/P0D3/CKOUT-LDC0/KS0* (Output)
V DD V DD
* Except LCD23/COM3, COM2, COM1, COM0
16
PD17P401
2. LIST OF FUNCTIONS
Product Name Item ROM
PD17401
12288 x 16 bits (Mask ROM)
PD17P401
12288 x 16 bits (PROM) 12288 x 16 bits 524 x 4 bits
Table reference area RAM Data buffers General registers System registers Register file General-purpose port registers Port registers LCD registers Instruction execution time Stack levels Generalpurpose ports Input/output ports Input ports Output ports * * * * * Display characters: Display positions : Character set : Character format : Character size :
4 x 4 bits 16 x 4 bits 12 x 4 bits 45 x 4 bits 45 x 4 bits 9 x 4 bits 36 x 4 bits 1.6 s (with 10 MHz crystal resonator connected) 7 levels (stack manipulation capability) 20 0 16 (Segment dual-function: 12) Max. 155 characters on one screen 14 lines x 24 columns 255 characters (user-programmable) 10 x 15 dots (2-dot space settable between characters) Vertical/horizontal size independently settable Vertical (14, 28, 42, 56H) Horizontal (2, 4, 6, 8 s)
Image display controller (IDC)
* * * LCD controller/driver
Output pins
: Blanking signal independently settable
At 1/3 duty, 1/3 bias: 36 segments, 3 common At 1/4 duty, 1/3 bias: 35 segments, 4 common Frame frequency : 250/n Hz (n = duty) Drive voltage : VDD Key source dual-function pins: 16 pins 12 pins usable as output port (4/4/4/4 pins independently settable) 2 systems (3 channels) 8-bit 3-wire: 2 channels 8-bit 2-wire: 1 channel 6 bits x 1 (successive approximation by software) 5 channels (maskable interrupts) External interrupts: 3 channels (INT0, INT1, VSYNC pins) Internal interrupts: 2 channels (modulo timer, serial interface 0) 3 systems Timer carry F/F (100 ms) 8-bit modulo timer (1/2/8/80 kHz) Clock 32 kHz counter (week, day, hour, min., sec. count)
* Serial interface A/D converter * * Interrupts * Timer
17
PD17P401
Product Name Item * * * * *
PD17401
Power-ON reset (when power is turned on) Reset via CE pin (CE pin: Low high) Power failure detection function
PD17P401
Reset
Standby Supply voltage Package
HALT mode : Release by CE, timer carry, interrupt, key input STOP mode: Release by CE or RLSSTOP pin 5 V +10 % 80-pin plastic QFP (14 x 14 mm)
18
PD17P401
3. ONE-TIME PROM (PROGRAM MEMORY) WRITE, READ AND VERIFY OPERATIONS
The program memory incorporated in the PD17P401 is 24576 x 8-bit electrically programmable one-time PROM. In normal operation, this PROM is accessed in a 16-bit word mode, but in program memory write, read and verify operations the memory is accessed in 8-bit word mode. In this case, the high-order 8 bits of the 16-bit word are allocated to an even address, and the low-order 8 bits to an odd address. For PROM write, read and verify operations, PROM mode is set and the pins shown in Table 3-1 are used. Address updating is performed by means of clock input from the CLK pin rather than by address input. Table 3-1 Pins Used in Program Memory Write, Read and Verify
Pin Name VPP CLK MD0 to MD3 D0 to D7 VDD1, VDD2
Function Program voltage (12.5 V) application Address update clock input Operating mode selection 8-bit data input/output Supply voltage (6 V) application
Writing to the on-chip PROM is performed using a PROM programmer and dedicated program adapter. The following types of PROM programmer and program adapter should be used: PROM programmer Program adapter AF-9703 (Manufactured by Ando Electric, Co., Ltd.) AF-9704 (Manufactured by Ando Electric, Co., Ltd.) AF-9808D (Manufactured by Ando Electric, Co., Ltd.)
3.1
PROGRAM MEMORY WRITE/READ/VERIFY OPERATING MODES
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD17P401 enters a program memory write/read/verify mode. This mode is one of the operating modes shown in Table 3-2 according to the setting of pins MD0 to MD3. Input pins not used in the program memory write/read/verify mode should be left open or connected to ground via a pull-down resistor (470 ) (see "PIN CONFIGURATION (2) PROM PROGRAMMING MODE"). Table 3-2 Program Memory Write/Read/Verify Operating Modes
Operating Mode Specification Operating Mode VPP VDD MD0 H L +12.5 V +6 V L H L X H H H H MD1 L H MD2 H H MD3 L H Program memory address zero-clear Write mode Read/verify mode Program inhibit mode
Remarks X: L or H
19
PD17P401
3.2 PROGRAM MEMORY WRITE PROCEDURE
The procedure for writing to program memory is as shown below, allowing high-speed writing. (1) Unused pins are connected to GND with a pull-down resistor. The CLK pin is driven low. (2) 5 V is supplied to the VDD pin. The VPP pin is driven low. (3) 5 V is supplied to the VPP pin after a 10 s wait. (4) The mode setting pin is set to the program memory address zero-clear mode. (5) 6 V is supplied to VDD, 12.5 V to VPP. (6) Program inhibit mode. (7) Data is written in 1 ms write mode. (8) Program inhibit mode. (9) Verify mode. If write is successful, go to (10), otherwise repeat (7) to (9). (10) (Number of times written in (7) to (9): X) x 1 ms additional writes. (11) Program inhibit mode. (12) Program memory address is updated (+1) by inputting 4 pulses to the CLK pin. (13) Steps (7) to (12) are repeated until the last address. (14) Program memory address zero-clear mode. (15) VDD/VPP pin voltage is changed to 5 V. (16) Power OFF. Steps (2) to (12) of this procedure are shown in the following Figure.
Repeated x times Reset Write Verify Additional write Address increment
V PP V PP VDD GND VDD + 1 VDD VDD GND X IN
D0-D7
Data Input
Data Output
Data Input
MD0
MD1
MD2
MD3
20
PD17P401
3.3 PROGRAM MEMORY READ PROCEDURE
(1) Unused pins are connected to GND with a pull-down resistor. The CLK pin is driven low. (2) 5 V is supplied to the VDD pin. The VPP pin is driven low. (3) 5 V is supplied to the VPP pin after a 10 s wait. (4) The mode setting pin is set to the program memory address zero-clear mode. (5) 6 V is supplied to VDD, 12.5 V to VPP. (6) Program inhibit mode. (7) Verify mode. When clock pulses are input to the CLK pin, data is output sequentially, one address per 4-input cycle. (8) Program inhibit mode. (9) Program memory address zero-clear mode. (10) VDD/VPP pin voltage is changed to 5 V. (11) Power OFF. Steps (2) to (9) of this procedure are shown in the following Figure.
V PP V PP VDD GND VDD + 1 VDD VDD GND
CLK
D0-D7
Data Output
Data Output
MD0
MD1
"L"
MD2
MD3
21
PD17P401
4. ELECTRICAL CHARACTERISTICS (PRELIMINARY)
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Supply Voltage PROM Supply Voltage Input Voltage Output Voltage Output Withstand Voltage Output Withstand Voltage Output Current High
VDD VPP VI VO VBDS1 VBDS2 IOH Except P1A0 to P1A3 P0A2, P0A3 P2A0 to P2A3 1 pin All pins 1 pin
-0.3 to +6.0 -0.3 to +13.5 -0.3 to VDD +0.3 -0.3 to VDD +0.3 VDD +0.3 18.0 -10.0 -20.0 10.0 20.0 450 -40 to +85 -55 to +125
V V V V V V mA mA mA mA mW C C
Output Current Low Total Loss Operating Temperature Storage Temperature
IOL
All pins PT Topt Tstg
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTICS
SYMBOL VDD1 VDD2
MIN. 4.5 3.5 2.2 2.2
TYP. 5.0 5.0 5.0
MAX. 5.5 5.5 5.5 5.5 500 16.0
UNIT V V V V ms V C
CONDITIONS CPU and IDC operating CPU operating, IDC stopped CPU and IDC stopped, clock timer operating Crystal oscillation stopped VDD = 0 4.5 V P2A0 to P2A3
Supply Voltage VDD3 Data Hold Voltage Supply Voltage Rise Time Output Withstand Voltage Operating Temperature VDDR tRISE VBDS Ta -40
+85
22
PD17P401
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 4.5 to 5.5 V)
STANDARD VALUES MIN. VDD1 Supply Voltage VDD2 VDD3 4.5 3.5 3.5 TYP. 5.0 5.0 5.0 MAX. 5.5 5.5 5.5 UNIT V V V IDC operating CPU operating Clock timer operating CPU operating, IDC stopped XIN pin sine wavve input (fIN = 10 MHz, VIN = VDD) Ta = 25 C CPU operating, IDC stopped, HALT instruction used 20 instruction executed per 1 ms XIN pin sine wave input (fIN = 10 MHz, VIN = VDD) Ta = 25 C Using power failure detection VDDR1 Data Hold Voltage VDDR2 2.2 5.5 V 3.5 5.5 V by timer F/F Crystal oscillation Using power failure detection by timer F/F Crystal oscillation stopped Data memory (RAM) hold Crystal oscillation stopped, IDDR1 4 6
CHARACTERISTICS
SYMBOL
CONDITIONS
IDD1
2.6
mA
Supply Current IDD2 2.0 mA
VDDR3
2.0
5.5
V
A
clock timer operating Ta = 25 C Crystal oscillation stopped, clock timer operating VDD = 5.0 V, Ta = 25 C Crystal oscillation stopped, clock timer stopped Ta = 25 C Crystal oscillation stopped,
IDDR2 Data Hold Current IDDR3
2
6
A
6
8
A
IDDR4
5
6
A
clock timer stopped VDD = 5.0 V, Ta = 25 C COM0, COM1, COM3 VDD = 5 V COM0, COM1, COM3 VDD = 5 V COM0, COM1, COM3 VDD = 5 V P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P2A0 to P2A3 P1B0 to P1B3 CE, INT0, INT1, HSYNC, VSYNC
VOMH1
3.1
3.3
3.5
V
Output Voltage Medium
VOMM1 VOML1 VIH1
2.3 1.4 0.7 VDD 0.6 VDD 0.8 VDD
2.5 1.6
2.7 1.8
V V V V V
Input Voltage High
VIH2 VIH3
23
PD17P401
STANDARD VALUES CHARACTERISTICS SYMBOL VIL1 Input Voltage Low VIL2 VIL3 IOH1 Output Current High IOH2 IOH3 IOL1 Output Current Low IOL2 IOL3 Input Current High IIH1 IIH2 IL1 Output Off Leak Current IL2 Output Withstand Voltage VBDS 0 500 16 V P2A0 to P2A3 P2A0 to P2A3 VOH = 12 V -1.0 -0.5 -0.1 1.0 1.0 1.0 0.1 0.1 1.3 1.3 500 -1.0 -0.8 0.3 VDD 0.2 VDD -5.0 -1.5 V V mA mA mA mA mA mA mA mA P1B0 to P1B3 CE, INT0, INT1, HSYNC, VSYNC * LCD0 to LCD35 VOH = VDD - 1 V P1B0 to P1B3 pulled high VOH = GND * LCD0 to LCD35 P2A0 to P2A3 XIN pulled low OSCIN pulled low P0A2, P0A3 VOL = 1 V VOL = 1 V VOL = 1 V VIH = VDD VIH = VDD VOH = VDD VOH = VDD - 1 V MIN. TYP. MAX. 0.3 VDD UNIT V CONDITIONS P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P2A0 to P2A3
* P0A2, P0A3, P0B0 to P0B3, P0C0 to P0C3, P1A2, P1A3, P1B0 to P1B3, P1C0 to P1C3, P1D0 to P1D3, IDC0, BLK0
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 4.5 to 5.5 V)
STANDARD VALUES CHARACTERISTICS SYMBOL fIN1 Operating Frequency fIN2 A/D Conversion Resolution A/D Conversion Total Error SIO External Clock Frequency 1.0 1.0 1.0 4 1.5 1000 kHz bit LSB kHz Ta = -10 to +50 C SIO0/SIO1 COM mode Ta = -10 to +50 C SCL, SCK0, SCK1 external clock frequency MIN. TYP. 10.0 MAX. UNIT MHz CONDITIONS Recommended CPU operation oscillation
24
PD17P401
REFERENCE CHARACTERISTICS
STANDARD VALUES CHARACTERISTICS Supply Current Output Current High SYMBOL IDD3 IOH4 MIN. TYP. 5 -0.2 MAX. UNIT mA mA CONDITIONS CPU and IDC operating VDD = 5.0 V, Ta = 25 C COM0, COM1, COM2 VOH = VDD - 1 V COM0, COM1, COM2 VOM = VDD COM0, COM1, COM2 VOM = 0 V COM0, COM1, COM2 VOL = 1 V
IOM1 Output Current Medium IOM2 Output Current Low IOL5
-20
A A
mA
20 0.2
DC PROGRAMMING CHARACTERISTICS (Ta = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.5 V)
CHARACTERISTICS Input Voltage High
SYMBOL VIH1 VIH2 VIL1
MIN. 0.7 VDD VDD -0.5 0 0
TYP.
MAX. VDD VDD 0.3 VDD 0.4 10
UNIT V V V V
CONDITIONS Except CLK CLK Except CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1 mA
Input Voltage Low VIL2 Input Leakage Current Output Voltage High Output Voltage Low VDD Supply Current VPP Supply Current ILI VOH VOL IDD IPP VDD -1.0 1.0 30 30
A
V V mA mA
MD0 = VIL, MD1 = VIH
Note 1 Ensure that VPP does not exceed +13.5 V including overshoot. 2 Ensure that VDD is applied before VPP and cut off after VPP.
25
PD17P401
AC PROGRAMMING CHARACTERISTICS (Ta = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.5 V)
CHARACTERISTICS Address Setup Time *2 (to MD0) MD1 Setup Time (to MD0) Data Setup Time (to MD0) Address Hold Time *2 (from MD0) Data Hold Time (from MD0) Data Output Float Delay Time From MD0 VPP Setup Time (to MD3) VDD Setup Time (to MD3) Initial Program Pulse Width Additional Program Pulse Width MD0 Setup Time (to MD1) Data Output Delay Time From MD0 MD1 Hold Time (from MD0) MD1 Recovery Time (from MD0) Program Counter Reset Time CLK Input High/Low-Level Width CLK Input Frequency Initial Mode Setting Time MD3 Setup Time (to MD1) MD3 Hold Time (from MD1) MD3 Setup Time (to MD0) Data Output Delay Time From Address *2 Data Output Hold Time From Address *2 MD3 Hold Time (from MD0) Data Output Float Delay Time From MD3 Reset Setup Time
SYMBOL tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV
*1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
UNIT
CONDITIONS
s s s s s
130 ns
s s
1.0 1.05 21.0 ms ms
s
1
s s
MD0 = MD1 = VIL
tM1H
tOEH
2
tM1H + tM1R 50 s tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tOR - - - - - - - 2 2 2 2 2 10 0.125 4.19
s s s
MHz
s s s s s
For program memory read For program memory read For program memory read For program memory read For Program memory read
tDAD
tACC
2
tHAD tM3HR tDFR tRES
tOH - -
0 2 2 10
130
ns
s s s
*1 Corresponding PD27C256 symbol. 2 Internal address incrementing (+1) is performed on the 3rd falling edge of CLK with 4 clock pulses as one cycle. Internal addresses are not connected to pins.
26
PD17P401
Program Memory Write Timing
t RES V PP V PP VDD GND VDD + 1 VDD VDD GND CLK D0-D7 tI MD0 t PW MD1 t PCR MD2 t M3S MD3 t M3H t M1R t M3H t M1R t MOS t OPW t DS t OH t DV t DF t DS
Data Input Data Output
t VPS
t VPS t XH
Data Input
t XL t DH t AH t AS
Data Input
Program Memory Read Timing
t RES V PP V PP VDD GND VDD + 1 VDD VDD GND t XH t VDS t VPS
CLK t XL t HAD D0-D7 t DV tI MD0 t DAD Data Output t M3HR t DFR
Data Output
MD1
"L" t PCR
MD2 t M3SR MD3
27
PD17P401
5. PACKAGE DIMENSION
28
PD17P401
APPENDIX. DEVELOPMENT TOOLS The following support tools are available for program development using the PD17P401.
Hardware Name Description The IE-17K is an in-circuit emulator which can be used with all models in the 17K series. For PD17P401 program development, the IE-17K is used in conjunction with the SE-17401 system evaluation board. As the IE-17K features RAM-based operation, immediate program additions and amendments can be made by connecting a console to the IE-17K. Moreover, use of the SIMPLEHOSTTM support software provides a higher-level program development environment. The SE-17401 is a PD17P401 system evaluation board used together with the IE-17K or by itself. The EP-17401GC is a probe for connection of the target system to the SE-17401. The EV-9200G-80 is a socket for connection of the target system to the EP-17401GC. Main PROM programmer unit. For the PD17P401, the programmer is used in conjunction with the AF-9808D special-purpose program adapter (Ver.5 or later should be used). Special-purpose program adapter for the PD17P401, used in conjunction with the AF-9703 or AF-9704. Ordering Code
In-circuit emulator (IE-17K)
IE-17K
SE board (SE-17401) Probe (EP-17401GC) Conversion socket (EV-9200G-80) PROM programmer (AF-9703) (AF-9704)
SE-17401
EP-17401GC
EV-9200G-80 AF-9703 AF-9704 (manufactured by Ando Electric, Co., Ltd.) AF-9808D (manufactured by Ando Electric, Co., Ltd.)
Program adapter (AF-9808D)
Remarks Please contact Ando Electric, Co., Ltd. for details of the PROM programmers and program adapter.
29
PD17P401
Software Name Description Host Machine OS Supply Medium 5-inch 2HD 3.5-inch 2HD 5-inch 2D 5-inch 2HD 3.5-inch 2HD 5-inch 2D 5-inch 2HD 3.5-inch 2HD 5-inch 2D Ordering Code
17K series assembler (AS17K)
AS17K is the assembler for use with the entire PC-9800 series 17K series. For PD17P401 program development, AS17K is used in conjunction with the device file (AS17401). IBM PC/AT TM
MS-DOSTM Ver.3.1 Ver.3.30 Ver.3.30A
S5A10AS17K
S5A13AS17K
PC DOSTM (Ver.3.1)
S7B11AS17K
Device file* (AS17401)
AS17401 is the device file PC-9800 series for the PD17401 and PD17P401, and is used together with the common 17K series assembler (AS17K). IBM PC/AT
MS-DOS Ver.3.1 Ver.3.30 Ver.3.30A
S5A10AS17401
S5A13AS17401
PC DOS (Ver.3.1)
S7B11AS17401
Support software (SIMPLEHOST)
SIMPLEHOST is software which implements the man-machine interface under MS-WINDOWSTM during program development using the IE-17K and a personal computer.
S5A10IE17K
MS-DOS PC-9800 series IBM PC/AT PC DOS
MSWINDOWS Ver.2.1 Ver.2.11
S5A13IE17K
S7B11IE17K
* Under development
SIMPLEHOSTTM is a trademark of NEC Corporation. MS-DOS and MS-WINDOWSTM are trademarks of MicroSoft Corporation. PC/ATTM and PC DOSTM are trademarks of IBM Corporation.
TM
30
PD17P401
31
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in the field where very high reliability is required including, but not limited to, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or those intend to use "Standard", or "Special" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Data processing and office equipment, Communication equipment (terminal, mobile), Test and Measurement equipment, Audio and Video equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Communication equipment (trunk line), Train and Traffic control devices, Industrial robots, Burning control systems, antidisaster systems, anticrime systems etc.

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